Job Title: Senior Digital Design Engineer Position: Full time permanent position Location: Bristol Salary Range: 50K : 80K GBP per annum depending on experience Client Information: My client is looking to strengthen their ASIC Digital Design team. Looking for bright candidates who have an enthusiasm and aptitude for working with ASIC chips. Designing chips for customers ranging from start:ups to blue chip companies, in industries including: automotive, medical, space and mobile technology companies. You will have a strong academic record, around 7:10 years' experience in industry working on ASIC developments and IP design. If you have at least one successful project as Technical Lead, a more senior position could be considered. You will possess a broad understanding of the IC design flow, strong 'hands:on' technical skills together with excellent communication skills and a desire to work in a customer facing organisation. Responsibilities: :Take full:flow ownership of all stages of the digital specification to RTL design flow, for complex ASIC blocks or full:chip :Work closely with customers and other teams to deliver projects on:time and to the required quality levels :Setup, run and maintain EDA tool flows, as needed, for each stage of the FE design flow :Keep up to date with all aspects of advanced ASIC FE design methodology and best:practise Essential Requirements: :1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University :Around 7:10 years' experience working in IC Development with a deep understanding of all aspects of ASIC FE design, from specification to RTL, and with a basic understanding of RTL to tape out flow :ASIC implementation skills (synthesis, DFT, timing closure) :Experience to lead one complex IP design and/or full ASIC design, from specification to full RTL :Specific expertise in the following technical areas : :RTL Design (VHDL or Verilog) :Functional verification : ideally a good knowledge of System Verilog and the use of techniques such as assertions and coverage driven verification :SoC knowledge : including the selection and integration of 3rd party IPs :Sound knowledge of SoC interconnect protocols, at least the Amba AHB plus one of the Amba AXI (AXI3, AXI4, AXI4:Lite, ACE, AXI5, AXI5:Lite,..) and n