Job Title: Senior Digital Design Engineer Position: Permanent Location: Cambridge, United Kingdom Salary Range: GBP 60K : GBP 80K DOE Client Information: Working to implement high performance AI inference solutions on FPGA. Contribute to IP library in SystemVerilog and build out complete FPGA design solutions for customers. Deliver highly performant, well tested and extensible code for some of the most widely deployed AI in modern data centers. Responsibilities: Writing and testing IP components in SystemVerilog for FPGA Building full applications for FPGA using our IP library Integrating with third party IP for external memory PCIe subsystems Extending IP verification code and integrating into automated test environments Working with software interface routines to support FPGA integration into the software stacks Learning about a range of Machine Learning inference optimization techniques Providing technical support for customer engagements Requirements: Masters degree in Engineering, Mathematics or other Scientific Discipline At least 5 years' experience generating clear, well:documented, and well:tested SystemVerilog, Verilog or VHDL code Experience simulating and verifying large RTL designs Worked with FPGA EDA tools such as Quartus or Vivado Worked with software languages such as C, C++, Python Familiarity with Linux development environments, version control and C I systems Experience of bringing up full FPGA designs and debugging on hardware Experience optimising RTL designs to achieve timing closure Desirable: Familiarity with neural network architectures :st